The illustrated embodiment of this invention employs magnetic tape recorders as data storage apparatus. In such prior tape storage subsystems of recent vintage, mechanical buffering of the tape was employed to enable high performance by such peripheral subsystems. For example, in high performance subsystems, so-called vacuum columns were employed as a mechanical buffer between a reel of tape and a transducing station. Such mechanical buffer allowed high acceleration rates of the tape thereby providing fast access to the data recorded on the tape. In lower performance systems, so-called "dancer arms", which are spring loaded tensioning arms, provide mechanical buffering with lower acceleration rates, hence longer access times. In the high performance area, the cost of manufacturing vacuum columns is quite high; further, the physical size of such tape recorders is relatively large. Accordingly, it is desired to use reel-to-reel tape drives and yet achieve short access times. Immediately, the idea of an electronic buffer for the data come to mind. In this regard, U.S. Patent R. A. Gregory et al. No. 2,960,683 shows an electronically buffered magnetic tape recorder, one buffer per tape recorder. In general, Gregory et al. show supplying signals to an electronic buffer during the same period of time that the magnetic tape is being accelerated. It should be noted that the tape recorder of Gregory et al. employs vacuum columns; therefore, even with vacuum columns higher performance was attempted.
In many recording systems, the length of record or block of signals is unknown. Since it has been common practice in data processing to have similar types of data in data sets, the lengths of records in each data set can be comparable; it is a reasonable expectation that a short record will be followed by another short record. Accordingly, by measuring a given record length, the expected record length of data yet to be recorded or read from a record medium can be predicted with reasonable accuracy. This observation of data processing data structures can be and is used to advantage by the present invention.
The operation of a data storage system often employs the use of a so-called MODE SET command, which for tape recording subsystems is similar to that described in the book "IBM Systems/360 and Systems/370 I/O Interface Channel to Control Unit Original Equipment Manufacturers' Information," Book GA22-6974-4, file number S360-S370-19, available from International Business Machines Corporation, Data Processing Division 1133 Westchester Avenue, White Plains, N.Y. 10604.
The reduction of storage access times at low cost has been a goal of all storage subsystems regardless of the type of data storage apparatus. For example, Eden et al. U.S. Pat. No. 3,569,938 shows an apparent store concept with a directory operated buffer for magnetic storage disk drives and magnetic tape storage drives. The buffer in Eden et al. is managed in the manner similar to that employed for a main memory in a data processing unit. The concept is to have a high performance (short access time) buffer masking the slow access times of tape recorders and magnetic storage disks. The general notion is to transfer data from the tape recorder or disk drive to the buffer. Upon receiving a request for some data from a using host, not only is the request data transferred from the tape recorder or disk drive to the buffer, but data surrounding the requested data is also transferred such that a next subsequent request from the host can most likely be satisfied from the buffer, i.e., exhibit enhanced performance. In all instances, the first request will be subject to the slow access times of the tape recorder or disk drive. The Eden et al. apparatus operates very efficiently for randomly accessed data wherein the method of managing the buffers determines total performance. There are instances when such random access is not always employed, such as in connection with tape recorders and other serial devices and in many instances, with disk drives as well. It is desired that the buffering enhance the access time in a maximal manner beyond that provided by Eden et al. in a storage subsystem.
One of the goals of the Eden et al. patent, is to make the host or user operation somewhat asynchronous with respect to the operation of the tape recorder/disk drive and for maximizing the asynchronous aspect of such operations which requires a relatively large electronic buffer. The larger the buffer, the greater the cost for the buffer as well as the greater the cost for controlling the buffer. Accordingly, it is desired to minimize the size of the buffer while still maximizing the asynchronous aspects of host to storage device operations and providing rapid access to data. For handling relatively large record sizes, the Eden et al. apparatus requires relatively large buffering for segmenting the operation in such a manner that undue complexity may be required in the storage subsystem--which which undue complexity tends to raise the cost of the subsystem.
In maximizing asynchronous aspects of operations of the host and a peripheral subsystem, the timing of the host and storage apparatus operations may drift a long way apart. That is, the operation of the peripheral subsystem may lag behind the operation of the host to such an extent that error recovery becomes difficult, if not impossible. On the other hand, the operation of the storage subsystem may actually lead the operation of the processor (in fetching data from the storage subsystem for example) such that buffer space is not well utilized. Accordingly, some means must be provided for limiting the asynchronous drift of operations. In multiprocessing, various computer processes within a central processing unit are also subject to asynchronous characteristics. A retry of programs and processes are preserved in central processing units, particularly in pipelined processes, by synchronizing program execution to data error recovery procedures. David W. Anderson et al. in U.S. Pat. No. 3,736,566 shows adding additional electronic circuits in a central processing unit for providing the ability to periodically establish a checkpoint. At each periodic checkpoint, a minimal amount of CPU status information is stored to permit processing to proceed with a plurality of instructions with the ability to enable the central processing unit to recover all the data and status at the time of the last periodic checkpoint. As stated above, it is desired to minimize the cost of the subsystem; therefore the periodic establishment in the subsystem could add undue costs. Accordingly, it is desired to provide prevention of the above described risk in operations at low costs for error recovery purposes. Checkpoint control has been implemented for input-output operations as shown by William E. Boehner et al. in U.S. Pat. No. 3,564,502. So-called "positional" information about an interrupted I/O device is communicated to the CPU as a result of an error in the channel. Such positional information about the I/O device is chosen in relation to the execution steps in a channel instruction so that a retry may be made of the channel instruction being executed at the time of the channel error. Such recovery action could be taken at the I/O device with the same channel instruction based upon the positional information existing at the time of channel error. With start-stop I/O devices, the apparatus of this patent enables a retry of a single erroneously executed channel command both during a chained command operation as well as during non-chained command operations. In accordance with this patent, the channel-I/O interface is monitored by a time-position signaling circuit which discretely cycles at different points in the execution of a channel instruction or command to an I/O device to generate codes representing respective time positions during the execution. At the moment of a channel error, the input to the signaling circuit is blocked, so that it continues to provide the position code existing at the time of the channel error. This particular apparatus requires one monitor per each operation. In a peripheral subsystem having a large plurality of devices with interleaved operations, such a system, which may be efficient for channel operations, becomes cumbersome and expensive for peripheral subsystems. Accordingly, even though input/output systems have employed time indicating positions for error recovery purposes, other means should be provided; particularly for a buffered peripheral subsystem.